Given time (and this is still very new) you probably will see chip manufacturers who are as open as they can possibly be, hell we may see completely open fabs at some point. The nitty gritty of transcoding and subsystems (and VMs) cooperating with each other to anyone can run anything they like without vendor lock-in and forced obsolescence is a technical thing. Article. Literally, it measures the rate of computation that can be delivered by a computer for every watt of power consumed. The politics is a bit of an issue I agree although the law is a lot clearer so easily subject to technical discussion and there is a fair degree of case law and science to lean on. Switzerland recently had its own scandal when it turned out one Swiss supplier of backdoored security products was owned by US and German intelligence. PC Apps; New RISC-V CPU claims recordbreaking efficiency per watt. For the vast majority of use cases there’s no real need to step away from. So I can see this chip stuff in the lower power market becoming very dominant, provided the applications can keep the processors cool. But I still don’t think you get it, RISC-V is a ISA, just an ISA. The RISC-V ISA—unlike x86, ARM, and even MIPS—is open and provided under royalty-free licenses. “World’s best CPU performance per watt”: Testing conducted by Apple in October 2020 using preproduction 13-inch MacBook Pro systems with Apple M1 chip and 16GB of RAM. Micro Magic Inc.—a small digital design agency in Sunnyvale, California—has ... Home PC Apps New RISC-V CPU claims recordbreaking efficiency per watt. I think we’re talking at cross purposes or have different goals or priorities in mind. So so long as the bitness, and subsets match, binary executables will carry over and run the same, and this is what you (or at least I) would want. I’m sure there will plenty of opportunity to revisit this in the future. Itani - December 4, 2020. I benchmarked it against the PineBook Pro. The world’s fastest CPU core in low-power silicon; The best CPU performance per watt of any computer chip ; The world’s fastest integrated graphics in a personal computer; Breakthrough machine learning performance with the Apple Neural Engine; The M1 chip is available in the new MacBook Air, 13-inch MacBook Pro, and Mac mini. Some scepticism and expertise is required and not everyone has the training or time or inclination for this. We need to give implementers the freedom to experiment and innovate, and RISC-V gives them a compatible ISA to do that. To put that in perspective, last year’s Snapdragon 865 with the 5th gen AI Engine featured 15 … For the M1, apple chose to implement x86 memory model in hardware rather than in software to avoid certain implied inefficiencies of software overhead. You say that you don’t care about implementation, which is fair enough given that many users don’t care either. I have some major reservations about all of these claims, mostly because of the lack of benchmarks that more accurately track real-world usage. If it’s something people can run with at some point I’m sure they will pipe up. They probably learned a lot from microsoft’s x86 emulation and decided to go with hardware assistance. The Snapdragon 888 also offers more energy efficient than the Snapdragon 865, with a 25% improvement in the CPU's performance-per-watt and 20% more … I’m sure someone will find a use. For example: https://nequalsonelifestyle.com/2020/12/06/mm-riscv-vs-rock64-arm/. For some or all of this to work via a fastpath or slowpath (could be hardware or software) the overall concepts and systems and regulations which enable this need to be worked out and specified. The Embedded Microprocessor Benchmark Consortium (EMBC) is a group with wide industry representation: Intel, Texas Instruments, ARM, Realtek, and Nokia are a few of its more notable and easily recognizable members. This is why I asked you to define what you meant, and ended up making a guess. In judging AMD vs Intel CPU performance per watt, It's impossible to overstate the importance of having the densest process node paired with … Huang 5.19GHz/1.1V.Later Ryzen 4700u SiFive Mark Santoro Lee Tavrow We're Ars As a FOSS user, what I want most is a very consistent and reliable boot strapping process where the owner is in control with no proprietary dependencies. So to summarize, there is binary compatibility so long as bitness and ISA subsets match, but that doesn’t doesn’t mean that you can just move from one CPU to another and assume that IO and the like all work the same. I’m more concerned about the abstract meta stuff like interoperability versus lock-in than what happens at the FAB end of the problem. I’m old enough to remember scenes on the news of Chinese wearing Mao suits and going everywhere on bicycle. Unsurprisingly, both parts produced more performance per watt when exercised with one work thread for each available CPU thread. In addition vendors are allowed to create their own modules to push functionality down to the processor level (for example this is what WD is doing). All we needed to do here was clone its GitHub repository, then issue a make command—optionally, with arguments XCFLAGS="-DMULTITHREAD=8 -DUSE_FORK=1" if we want to test on multiple threads/cores at once. None of this made much of a dent in the Micro Magic's commanding lead in power efficiency. Micro Magic adviser Andy Huang claimed the CPU could produce 13,000 CoreMarks (more on that later) at 5GHz and 1.1V while also putting out 11,000 CoreMarks at 4.25GHz—the latter all while consuming only 200mW. If you've got access to a Linux system, it's pretty easy to download, compile, and run CoreMark yourself. Don’t beat yourself up, the M1 did well in some benchmarks and poorly in others. Lobbyists and vested interests with deep pockets and now too many politicians spend more time leaning on marketing than creating good legal frameworks and policy based on the public interest. I’m a bit sceptical of RISC-V as it seems more of an American thing, Oh china is biting pretty hard on RISC-V as well. The main problem at the abstract level is core versus extended functionality. The AMD Embedded Ryzen V2000 family features up to eight 'Zen 2' CPU cores and seven GPU compute units, built on a 7nm process. I don’t know enough about the engineering to know what is covered by patent versus trade secret to know how much or little they can open up and this is before international security and trade wars are considered. I do agree with your comments on why the Chinese are using RISC-V and other CPUs and what they are used for. Performance per watt refers to the ratio of peak CPU performance to average power consumed using select industry standard benchmarks. A lot was identical differing only in implementation where implementations certified for industrial use took less shortcuts and were pixel accurate, and retail implementations were a bit quick and dirty in places and sacrificed accuracy for performance reasons. 2020 is the year of a global pandemic that forced many of us to work from home. Ars may earn compensation on sales from links on this site. Use of and/or registration on any portion of this site constitutes acceptance of our User Agreement (updated 1/1/20) and Privacy Policy and Cookie Statement (updated 1/1/20) and Ars Technica Addendum (effective 8/21/2018). Oops. The lesson of Apple’s M1 is that you don’t need new instructions (to the best of our knowlege there are no additional instructions in the M1 for that), but a different Mode to implement the intel consistency model so the code would execute more like an x64 processor. One AMD Ryzen Embedded V2000 Series processor can provide twice the multi-threaded performance-per-watt, up to 30 percent better single-thread CPU performance and up to 40 percent better graphics performance over the previous generation. Micro Magic intends to offer its new RISC-V design to customers using an IP licensing model. Small world. It may be RISC-V benefits from some extentions to facilitate co-existance of OS and portability. Exactly! At the maximally performant 5GHz clock, it manages just over a third of their performance. Apple's first stab at a small form factor desktop and laptop processor offers impressive performance-per-watt metrics. Sorry but I don’t get what you are saying. The numbers support that and do show ARM is more efficient in doing the tasks at hand, in this case Geekbench 5. By. For people with use case and power envelopes which match the capabilities either would be useful if Arstechnica tests are accurate. This is true. This can be annoying when you try to have an objective conversation, but that is human nature I suppose, haha. This may well be the same tactic for the processors, you can imagine an array of these devices working at low bandwidth/demand feeding a centralised conventional chip with heavily curated data, in effect doing all the housekeeping which could massively improve performance and efficiency. Included in these lists are CPUs designed for servers and workstations (such as Intel Xeon and AMD EPYC/Opteron processors), desktop CPUs … Performance per watt refers to the ratio of peak CPU performance to average power consumed using select industry standard benchmarks. The simplicity of the design—RISC-V requires roughly one-tenth the opcodes that modern ARM architecture does—further simplifies manufacturing concerns, since RISC-V CPU designs can be built in shuttle runs, sharing space on a wafer with other designs. Even at its efficiency-first 3GHz clockrate, the Micro Magic CPU outperformed a Qualcomm Snapdragon 820. But is ... What is performance per watt? Micro Magic adviser Andy Huang claimed the CPU could produce 13,000 CoreMarks (more on that later) at 5GHz and 1.1V while also putting out 11,000 CoreMarks at 4.25GHz—the latter all while consuming only 200mW. What you are talking about is implementation… I think. The industry then broke down into industrial use versus game use. Sign up or login to join the discussions! Ad Choices. We're also still taking a pretty fair amount of Micro Magic's claims at face value. For the Apple, I only had access to whole-system power draw, so I subtracted the "desktop idle" power draw from the "under test" power draw. PassMark Software has delved into the thousands of benchmark results that PerformanceTest users have posted to its web site and produced nineteen Intel vs AMD CPU charts to help compare the relative speeds of the different processors. I don't have access to anything nearly as fine-grained as turbostat for the Apple M1, so for that platform I took whole-system power draw at the wall and just plain subtracted the reading at desktop idle from the sustained reading while under test. Ultimately, while I have good vibes from RISC-V, I still fear that its openness could be subverted by corporate influences like has happened with most of our ARM devices. Read our affiliate link policy. I am not saying anything about politics, but their policy of favoring home grown processors internally is creating great incentive to be competative. New RISC-V CPU claims recordbreaking performance per watt Thom Holwerda 2020-12-04 Hardware 26 Comments Ars Technica summarises and looks at the various claims made by Micro Magic about their RISC-V core. This is enough to let us know that the Micro Magic chip in its current form isn't a world-class competitor for traditional ARM and x86 CPUs in phone or laptop applications—but it's much closer to them than previous RISC-V implementations have been. I’m not getting into whataboutary or having words put in my mouth and as I think we’ve covered everything this is probably a good place to end discussion. Today, Micro Magic announced another breakthrough, promising “the world’s highest performance/power 64-bit RISC-V core at 110,000 CoreMarks/Watt.” The Micro Magic RISC-V processor used in today’s 3GHz demo appears to be essentially the same as the similarly unnamed core in the EETimes demo running at 5GHz and 13,000 CoreMarks at 1.1V. That's triple the efficiency of the Ryzen 4700u running single-threaded and a little better than par with it when the Ryzen's running an optimally multithreaded workload. But isn’t it OK for those to be a subset of the whole, so consumers can choose, and still know that code will run on those processors transparently as proprietary implementations? I’ve been involved on a bit of this stuff for the printed SolarPV, in that sector the target is $1/m² but the cost of what you can do in that square meter doesn’t rise proportionally with the density of devices on the film. I’d really like to see RISC become the platform of choice for FOSS, but we’ve got a bit of a catch-22: we need manufacturers to make these products viable, yet all too often when they do it comes will strings attached, proprietary blobs, and owner restrictions. — AMD Ryzen Embedded V2000 Series processors deliver double the cores 1, up to 2x the performance-per-watt 2 and an estimated 15 percent IPC uplift 3 over the previous generation —. There are completely open and inspectable implementations of RISC-V that I think satisfy what you want, but at it’s core RISC-V is intended to spur innovation, research, implementations, etc by providing a common, IP-Free ISA. Because RISC-V doesn’t dictate the implementation, extra instructions for emulation aren’t guaranteed to matter. We first noticed Micro Magic's claims earlier this week, when EE Times reported on the company's new prototype CPU, which appears to be the fastest RISC-V CPU in the world. GCC and LLVM collaborated on what they wanted from a compiler implementation level, but anyone is fine to define their own (as with any other CPU). Where the balance lies is a question between RISC-V, OS vendors and IHVs, and consumers and I think there is some scope for discussion. I agree we are unlikely to see any movement on this although there are plenty of technical people who are interested. ... offers big improvements in performance per watt … Micro Magic Inc.—a small electronic design firm in Sunnyvale, California—has produced a prototype CPU that is several times more efficient than world-leading competitors, while retaining reasonable raw performance. (It's worth noting that we had no way to run CoreMark on the M1's slower, less battery-hungry Icestorm cores only.). RISC-V could implement an x86 compatibility mode like apple, but for users like myself though, I don’t really see much benefit in emulating x86 code and I suspect most people who find RISC-V appealing aren’t that interested in emulating x86 either. I’m bothered about the general purpose baseline versus the use case specific implementation issues. RISC-V endorsed the Wishbone bus for systems on a chip but vendors aren’t required to use it. It’s the same with politics. I don’t know really being only casually familiar with it. 0. What the Chinese are up to at a hardware level is a response but I’m fearing the Chinese are basically taking an open system and (like NVidia who are ten times worse than AMD/ATI ever were) are effectively closing it in practice. In other words, Micro Magic's prototype CPU is both significantly faster and tremendously more power-efficient than a reasonably modern and still very capable smartphone CPU. When I say modular I mean that if you don’t want floating point, you can leave out that module, etc. It’s surprisingly difficult to convince people to detach themselves from preconceived opinions and look at the data sometimes.